Digital integrated circuit design faces several challenges due to the rapid development of VLSI manufacturing and increasing integration density. Clock-tree synthesis，a key part of digital back-end design，faces the issues of reduced iterative efficiency and slower convergence. In this study，we proposed the synchronous clock-tree hierarchical partitioning and clustering(SC-HPC)algorithm to overcome these challenges. The SC-HPC algorithm divides the original register clustering process into two steps:coarse clustering and fine clustering. The coarse clustering phase partitions physically placed the registers into N macro-clusters，with subsequent refinement tasks for these clusters being allocated to a user-configurable thread pool for parallel processing acceleration. Fine clustering further partitions the registers based on the buffer maximum fan-out rule. The experimental results indicate that the SC-HPC algorithm reduces the number of buffers by over 30% and runtime by over 20% when compared with the existing methods.