In this study， we designed an EEG analog front-end readout circuit based on 180 nm CMOS technology. The instrumentation amplifier employs an AC-coupled capacitive feedback topology integrated with DC servo loop，ripple suppression loop，and global chopper modulation，thereby achieving both high-pass characteristics and a gain of 40 dB. The low-pass filter employs a switched-capacitor structure to implement precise cutoff frequency for high-frequency interference suppression，along with the correlated double sampling technique to eliminate offset voltage. The programmable gain amplifier adopts the flipped-capacitor principle to improve low-frequency response and incorporates an enhanced class-AB output stage to drive the asynchronous timing SAR-ADC. Additionally，the design includes the power management unit and right-leg drive circuit. Implemented in fully differential architecture， the post-layout simulation results indicate that the analog front-end achieves a bandwidth of 0. 075–174 Hz，adjustable gain from 56 to 86 dB，equivalent input impedance up to 255 MΩ，CMRR exceeding 180 dB，and input-referred noise of58.4 nV/ Hz(@100 Hz).