In this study，we designed a low-power successive approximation register analog-to-digital converter(SAR ADC)with switchable 8/12-bit resolution for physiological signal processing applications. We implemented a comparator time-division control logic with a low duty cycle clock to achieve a high-precision pre-amplified latch comparator and a low-power fully dynamic comparator operating in a time-division mode，thereby reducing the power consumption. The DAC employs a switchable bit-level energy-saving scheme based on three-level capacitors，thereby minimizing the switching energy and the number of unit capacitors. We designed a synchronized control logic based on dynamic SAR logic，which can eliminate leakage，to ensure stable system operation under low-power conditions. The design and post-simulation were performed using a 0. 18 μm CMOS process. At a sampling rate of 25 kS/s and an input signal rate of 11. 91 kS/s，with supply voltages of 1. 2 V/1. 4 V，the power consumption in the 8/12-bit mode is 0. 87/1. 2 μW，SFDR is 53. 8/79. 2 dB，FOM is 203. 2/19. 5 fJ/(conv-step)，and ENOB reaches 7. 43/11. 26 bits.