In the conventional 2-bit/cycle SAR ADC，2N additional unit capacitors are required to increase the speed. In this study，we proposed a 2-bit/cycle high-speed SAR ADC with comparator interleaved based on the 40 nm CMOS process to overcome this limitation. The proposed structure reduces the usage unit capacitors of the CDAC by 50% by automatically switching comparators of different sizes in the last comparison cycle，thereby achieving an equivalent reduction in the reference voltage. Furthermore，the proposed comparator speed feedback system can increase the speed of the comparator when the input voltage difference is low. The noise and distortion are reduced by using two-stage grid voltage bootstrap and introducing a compensating capacitor in the sampling and holding circuit. The simulation results indicate that the resolution of this ADC is 10-bit，a sampling frequency of 700 MS/s，a signal-to-noise ratio(SNDR)of 55.05 dB，a spurious-free dynamic range(SFDR)of 67. 27 dB at Nyquist input frequency， and an overall power consumption of 2. 91 mW. The Walden FoM is 9. 20 fJ/conv.