To address the high resource consumption，low concurrency，and timing convergence challenges found in traditional parallel timers，a parallel timer implemented on an application-specific IC(ASIC)is proposed to solve the parallel timing problem in high-concurrency scenarios. The proposed design is based on three main concepts: First，a hierarchical timing architecture splits the long-duration timing task into up to three independent sub-tasks， combined with multiple timer monitoring modules to achieve precise management of all timing tasks. Second，data storage in on-chip static RAM significantly reduces circuit area and dynamic power consumption. Third，multi-level parallel processing greatly improves task processing efficiency. Logic synthesis was performed using DC tools，and a verification environment was built to test and validate the design in various scenarios. The results show that，with appropriate parameter configurations，the timer maintains high accuracy，low dynamic power consumption，small area， and high scalability，with an average absolute percentage error of less than 0. 1% in most scenarios，even when concurrency reached 4 096.