偏压温度应力下 SiC MOSFET器件可靠性劣化的物理机制
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(1.大连理工大学控制科学与工程学院,辽宁大连 116024; 2.工业装备智能控制与优化教育部重点实验室(大连理工大学),辽宁大连 116024)

作者简介:

刘起蕊(2001.),女(汉族),河北廊坊人,硕士研究生,从事 SiC半导体器件研究工作。王德君(1966.),男(汉族),吉林德惠人,博士,教授,博士生导师,从事半导体器件物理与工艺、半导体缺陷物理研究。通信作者。

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TN386. 1

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Physical Mechanisms of Reliability Degradation in SiC MOSFET Devices under Bias Temperature Stress
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(1. Dalian University of Technology,School of Control Science and Engineering,Dalian,Liaoning 116024,P. R. China;2. Ministry of Education,Key Laboratory of Intelligent Control and Optimization for Industrial Equipment(Dalian University of Technology),Dalian,Liaoning 116024,P. R. China)

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    摘要:

    栅氧界面陷阱是引起 SiC MOSFET可靠性劣化的主要根源。基于 N型 4H-SiC MOSFET结构,系统地研究了偏压温度应力下栅氧界面陷阱对器件电学特性及可靠性的影响。研究结果表明,受主陷阱密度和能级会显著影响电学特性,具体表现为阈值电压正向漂移、导通电阻增大以及 C-V特性曲线的变化;而施主陷阱对电学特性的影响较小,主要反映在 C-V曲线积累区的电容变化。高温下,浅能级受主陷阱对载流子捕获能力显著减弱,但深能级受主陷阱仍保持较强的捕获能力。此外,热载流子注入效应与栅极应力大小和时间相关,随着栅偏压增大、应力时间增加,界面陷阱密度增加、范围扩大,影响器件电学特性,显著劣化长期可靠性。

    Abstract:

    Gate oxide interface traps are the primary cause of reliability degradation in SiC MOSFETs. In this study,based on the structure of N-type 4H-SiC MOSFETs,the impact of gate oxide interface traps on the electrical characteristics and reliability of the devices under bias temperature stress was systematically investigated. The research results indicated that the density and energy levels of acceptor traps significantly affected the electrical characteristics, specifically manifested as a positive shift in the threshold voltage,an increase in the on-resistance,and changes in the C-V characteristic curves. The influence of donor traps on the electrical characteristics was relatively minor,primarily reflected in the capacitance changes in the accumulation region of the C-V curves. At high temperatures,the carrier capture capability of shallow-level acceptor traps significantly weakened; however, deep-level acceptor traps maintained a strong capture capability. Additionally,the hot carrier injection effect was related to the magnitude and duration of the gate stress. Increasing the gate bias and stress time led to an increase in the interface trap density and their range expands, affecting the electrical characteristics of the device and significantly degrading long-term reliability.

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  • 收稿日期:2025-03-20
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  • 在线发布日期: 2025-08-22
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