To address the problem of solder joint cracking in low-cost chip carrier (LCCC) packaging devices under temperature cycling loads, we first analyze the failure phenomenon and mechanism and establish a finite element model for simulating failure stress. Two stress relief schemes for the printed circuit board (PCB) are proposed to reduce the thermal stress caused by the mismatch in the coefficient of thermal expansion (CTE) between packaging materials. The impact of different hole sizes in the single-hole scheme and different hole quantities for the array-hole scheme on the thermal fatigue life were analyzed and studied. Subsequently, a novel stacked solder column stress buffering scheme is proposed to mitigate the impact on PCB layout density. Sensitivity analysis was performed for different stacked board thicknesses and solder column spacings. The results indicate that larger opening areas, thinner stack boards, and denser solder columns effectively reduce the solder joint stress, enhance the solder joint thermal fatigue life, and significantly improve the thermal fatigue reliability of LCCC packaging devices.