A behavioral model of a read-write control system for synchronous-pipelined static random access memory (SRAM) was designed. The control signals and working timing requirements of the SRAM chip were analyzed, and a behavioral model of a read-write system for the SRAM chip was built using Verilog hardware description language. The system consists of three components, the host, main controller, and memory chip, with the main controller further comprising two submodules, the signal source generator and data transceiver controller. The system behavioral model was simulated and verified using ModelSim software. The simulation results show that the system control model can read and write the SRAM chip correctly in non-burst (regular), linear burst, and interleaved burst operation modes. The number of source control signals from the host decreases to the minimum; thus, the read and write control procedure is considerably simplified. The data are sampled and transmitted with the double edges of the system clock, thus improving the stability of the system.