一种高PSR低静态电流LDO设计
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(南京邮电大学 集成电路科学与工程学院, 南京 210023)

作者简介:

王天凯 (2000—),男(汉族),安徽池州人,硕士研究生,研究方向为模拟IC设计。 张 瑛 (1980—),男(汉族),安徽黄山人,教授,硕士生导师,研究方向为模拟与射频IC设计。通信作者。

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中图分类号:

TN433; TM44

基金项目:

国家自然科学基金面上项目(61971240)


Design of High PSR and Low Quiescent Current Low-Dropout Linear Regulator
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(College of Integrated Circuit Science and Engineering, Nanjing Univ. of Posts and Telecommun., Nanjing 210023, P. R. China)

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    摘要:

    设计了一种基于0.18 μm BCD工艺的高电源抑制(PSR)低静态电流低压差线性稳压器(LDO)。详细分析了多条电源噪声传递路径对系统PSR的影响。为优化系统中低频段PSR,设计了一种双轨供电的三级误差放大器。此外还引入了预稳压单元,降低了电压基准模块对系统低频段PSR的影响。为降低系统的静态电流,设计了一种基于耗尽管的超低静态电流电压基准。仿真结果表明,该LDO在不同输出电压下静态电流仅5 μA,并且在250 mA负载电流内PSR<-110 dB @1 kHz,PSR<-55 dB @1 MHz。

    Abstract:

    A low-dropout linear regulator with high power supply rejection(PSR) and low quiescent current was designed using a 0.18 μm BCD process. A detailed analysis was conducted on the effects of multiple power ripple propagation paths on the PSR of the system. A three-stage error amplifier with a dual-rail power supply was designed to optimize the PSR at low-middle frequency. Additionally, a pre-regulator was introduced to reduce the influence of the voltage reference module on the low-frequency PSR of the system. An ultra-low quiescent current-voltage reference based on the depletion transistor was designed to lower the quiescent current of the system. Simulation results demonstrate that the quiescent current can be as low as 5 μA at different output voltages, and within a load current range of 250 mA, the PSR is below -110 dB at 1 kHz and below -55 dB at 1 MHz.

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  • 收稿日期:2023-06-14
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  • 在线发布日期: 2024-06-27
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