一种基于分段电阻的低功耗电流舵DAC
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(大连理工大学 集成电路学院, 辽宁 大连 116620)

作者简介:

刘 照(1999—),男(满族),江苏南京人,硕士研究生,从事模拟集成电路设计和测试研究工作。 常玉春(1973—),男(汉族),吉林长春人,博士,教授,研究方向为CMOS图像传感器。通信作者。

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中图分类号:

TN432; TN792

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大连市科技创新基金资助项目(2020RT01); 2022年产业基础再造和制造业高质量发展专项资助项目(TC220A04A-49)


Low-Power Current-Steering DAC Based on Segmented Resistors
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(School of Integrated Circuits, Dalian University of Technology, Dalian, Liaoning 116620, P. R. China)

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    摘要:

    基于 SMIC 180 nm 标准 CMOS 工艺,设计了一款面积仅为320 μm×150 μm的10 bit分段式电流舵数模转换器(DAC)。该设计采用“5+5”式分段,通过电阻实现高位子DAC的量化阶梯,从而减小高位子DAC所需电流。与原始的电阻量化结构相比,改变电流流向,节约了一半的电流源数量。同时通过校准电阻的方式,有效校准了结构中存在的特殊非理想特性。仿真验证结果表明,本分段电流舵DAC微分非线性(DNL)和积分非线性(INL)最大值分别为0.09 LSB和0.34 LSB,无散杂动态范围为64.52 dB,功耗为8.58 mW。与传统结构相比,该结构面积减小约80%,有效减小分段式电流舵DAC的功耗以及面积。

    Abstract:

    An innovative 10-bit segmented current-steering digital-to-analog converter (DAC) was designed through an SMIC 180 nm standard CMOS process, utilizing a minimalistic footprint of 320 μm×150 μm. The "5+5" segmentation architecture achieves a high-position quantization ladder of the DAC through resistors, thus minimizing the total current. Compared with the original resistance quantization structure, this innovative structure alters the current flow direction, conserving half the current sources. Furthermore, the distinct non-ideal characteristics inherent in this novel structure are rectified effectively using a calibration method, traditionally employed in resistor string DACs. Simulation results show that the differential nonlinearity (DNL) and integral nonlinearity (INL) of the DAC are confined to 0.09 and 0.34 LSB, respectively, while achieving a spur-free dynamic range of 64.52 dB and a power consumption of 8.58 mW. Compared with conventional structures, this structure demonstrates an approximate 80% reduction in the area consumption and mitigates the power and area of the segmented current-steering DAC.

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  • 收稿日期:2023-07-25
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  • 在线发布日期: 2024-06-27
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