An ultra-wideband six-bit digital attenuator operating at frequencies ranging from 10.4 GHz to 28 GHz was designed and implemented in SMIC 40 nm CMOS process. The attenuator utilized an embedded switching-type structure, with the six-bit attenuation unit designed in three different topologies, T-type, bridge-T-type, and π-type. This six-bit attenuator achieves a step attenuation of 0.5 dB and a dynamic attenuation range of 31.5 dB. By incorporating a large attenuation amplitude compensation circuit and a cascaded structure of attenuation bits with excellent matching characteristics, the attenuator achieves a flat 64-state attenuation across the frequency range of 10.4 GHz to 28 GHz. The pre-simulation insertion loss of the attenuator ranges from 1.73 dB to 2.08 dB, while the post-simulation insertion loss ranges from 4.32 dB to 6.31 dB. Furthermore, the input and output return losses of all 64-states are less than -10 dB.