(北京智慧能源研究院 先进输变电技术国家重点实验室, 北京 102200)
(State Key Laboratory of Advanced Power Transmission Technology,Beijing Institute of Smart Energy, Beijing 102200, P. R. China)
介绍了一种在JFET区域采用浅槽N型重掺杂降低器件比导通电阻与开启损耗的1 200 V碳化硅平面栅MOSFET器件。采用浅槽结构设计,减小了器件栅源电容CGS及栅漏电容与栅源电容比值CGD/CGS,降低了器件的开启损耗。浅槽下方采用的N型重掺杂使得器件反型层沟道压降明显提高,使器件获得了更低的比导通电阻。仿真结果表明,相比于平面栅MOSFET器件,开启损耗降低了20%；相比于平面栅MOSFET与分裂栅MOSFET,器件比导通电阻分别减小了14%和17%。
The 4H-SiC MOSFET with a shallow trench is designed and studied to reduce the specific on-resistance and turn-on loss. The proposed structure shows a lower CGS and CGD/CGS because of the shallow trench in the JFET region. By introducing the highly doped N+ region under the trench, the electron quasi-fermi potential across the inversion layer along the interface of SiC/SiO2 is increase, which improves the current capability of the MOSFET and reduce the specific on-resistance Ron. And the simulation results demonstrate that the specific on-resistance of the proposed structure is reduced by 14% and 17.8% compared with that of the planar MOSFET and split gate MOSFET, respectively. Besides, the turn-on loss is also reduced by 20% compared with that of the planar MOSFET.