(江南大学 电子工程系 物联网技术应用教育部工程研究中心, 江苏 无锡 214122)
史世昕 (1998—),女(汉族),山西晋城人,硕士研究生,研究方向为模拟集成电路设计。 虞致国 (1979—),男(汉族),江西万年人,教授,博士,研究方向为超大规模集成电路设计。通信作者。
(Technology Engineering Research Center of IoT Technology Applications (Ministry of Education), Department of Electronic Engineering, Jiangnan University, Wuxi, Jiangsu 214122, P. R. China)
针对传统四相时钟发生电路产生的时钟波形信号易发生交叠、驱动电荷泵易发生漏电等问题,提出了一种占空比可调四相时钟发生电路。电路在每两相可能出现交叠的时钟信号之间都增加了延时单元模块,通过控制延时时间对输出时钟信号的占空比进行调节,避免了时钟相位的交叠。对延时单元进行了改进,在外接偏置电压条件下,实现了延时可控。基于55 nm CMOS工艺的仿真结果表明,在10~50 MHz时钟输入频率范围内,该四相时钟发生电路可以稳定输出四相不交叠时钟信号,并能在1.2 V电压下驱动十级电荷泵高效泵入11.2 V。流片测试结果表明,该四相时钟发生电路能够产生不相交叠的四相时钟波形,时钟输出相位满足电荷泵驱动需求。
Aiming at the problems of the traditional four-phase clock generator circuit, such as the overlapping of clock waveform signals and the leakage of charge pump, a new four-phase clock generator circuit with adjustable duty cycle is proposed. The circuit added a delay unit module between the clock signals that may overlap in each two phases, and adjusted the duty cycle of the output clock signal by controlling the delay time to avoid the overlap of the clock. Additionally, the delay unit was adapted to realize the controllable delay under the condition of external bias voltage. The simulation results based on a 55 nm CMOS process show that the four-phase clock generator circuit can output four-phase non-overlap clock signal stably in the clock input frequency range of 10-50 MHz, and can drive the 10-stage charge pump to pump 11.2 V efficiently at a supply voltage of 1.2 V. The tested results obtained from fabricated circuits show that the four-phase clock generator circuit can produce non-overlapping four-phase clock waveforms, and the clock output phase can meet the driving requirements of the charge pump.