A clock IP circuit structure suitable for 1.8/2.5/3.3 V wide power supply range is proposed. In order to suppress the influence of the reset pulse signal of the frequency and phase detector (PFD) on the performance of the charge pump (CP) when the power supply changes, a constant reset pulse width generation circuit is proposed. An ultra-low mismatch CP was used to increase the output current matching. The IUP/IDN current mismatch was less than 0.09% when the control voltage varied within a range of 0.2-(VDD-0.2) V. At the same time, a ring oscillator (RO) with symmetrical load structure was introduced to suppress the impact of power supply change on the loop performance. The whole circuit was designed and simulated in SMIC 180 nm CMOS process, and the output frequency was 100-500 MHz. The simulation results show that when the input reference frequency is 50 MHz and the output frequency is 250 MHz, the power consumption is 8.2/12.5/18.4 mW at 1.8/2.5/3.3 V supply voltage, respectively, the reference spurious is lower than -74 dBc, and the output rms jitter is 1.8 ps.