An asymmetric Doherty power amplifier (DPA) with a saturated output power of 44 dBm and an output back-off of 9 dB was designed in a GaN process, with a front driving power amplifier (PA) added for gain increase. Afterwards, by optimizing the impedance matching network of main PA, the λ/4 impedance conversion line could be removed. The output impedance of auxiliary PA was replaced by RC network equivalently, and the phase of output matching was maintained at 0°, thereby ensuring high resistance state during turn-off. Also, the optimal impedance at closing point was directly selected as 50 Ω,thus removing the λ/4 impedance conversion line. The simulation results show that when considering the frequency band of 3.3-3.6 GHz, a saturated output power, a power gain, and a power added-efficiency (PAE) of the proposed DPA are higher than 44 dBm, 25 dB, and 50%, respectively. Besides, PAE can be above 34.7% at the output back-off of 9 dB. In addition, the chip size of DPA is 3.4 mm*3.3 mm, and that of driving PA is 1.5 mm*1.7 mm.