(1. 北京大学 集成电路学院, 北京 100871;2. 北京微电子技术研究所, 北京 100076)
(1. School of Integrated Circuits, Peking University, Beijing 100871, P. R. China;2. Beijing Microelectronics Technology Institute, Beijing 100076, P. R. China)
折叠式共源共栅和Class AB(FC-AB)结构的运算放大器被广泛研究和使用,但是其结构应用的多变性使设计者难以快速准确地设计出符合要求的电路。文章提出了一种标准化的运算放大器设计流程,设计者可以根据应用需求快速灵活地设计目标电路。以电流分配作为设计流程的起始点和调整点,以核心参数作为判据或约束项,进行迭代优化,最终通过相关电流和跨导确定器件尺寸。以流程图形式提出了低噪声运放的设计流程,关键器件尺寸的理论值和设计值平均误差为11.48%。根据该流程设计了一种低噪声运放,并采用0.18 μm CMOS工艺进行了加工。运放关键电学参数都满足设计要求,其等效输入噪声为10.8 nV/√Hz,与目标值偏差1.8%。
Folded cascode and Class AB topology (FC-AB) operational amplifiers are widely studied and used. However, it is still difficult for designers to build up a specific operational amplifier quickly and accurately due to various applications. In order to solve this problem, this paper presents a quasi-standard design procedure of operational amplifiers for designers who can complete the circuit design by following this procedure. Current distribution was determined as the starting point and the adjustable point in this design procedure, and the most concerned parameter was set as primary constraint and optimized through multiple iterations. At last, the sizes of devices were obtained by corresponding current and trans-conductance. The design procedures for low noise operational amplifiers have been presented in the form of flow charts. The average error between the theoretical values and the final design values of key device sizes were 11.48%. To verify the feasibility of the design procedure, an operational amplifier was designed by using this design procedure and fabricated with a standard 0.18 μm CMOS process. The concerned electrical characteristics are all met with the design requirements. Its input-referred noise is 10.8 nV/√Hz, which differs from the target value by only 1.8%.