A low-phase-noise cascaded dual phase-locked loop millimeter-wave frequency synthesizer was designed in a 65 nm CMOS technology. A two-stage phase-locked loop cascaded structure was adopted to reduce the influence of bandwidth constraints on the phase noise in band and out of band of the single-stage system in millimeter-wave frequency synthesizer. The vernier structure was adopted in time-to-digital converter to improve the quantization linearity during the time-to-digital convert under PVT changes. The automatic loop gain control technology was used in digital loop filter to adaptively adjust the loop bandwidth to improve the performance of the frequency synthesizer. The noise circulating technology was adopted in oscillator to reduce the injected noise of resonator so as to improve the phase noise of oscillator. The post-simulation results show that the frequency range of the frequency synthesizer is 22-26 GHz under a supply voltage of 1.2 V. When the output frequency is 24 GHz, the phase noise is -104.4 dBc/Hz @1 MHz, and the power consumption is 46.8 mW.