A 25-28 Gbit/s optical receiver circuit with adaptive equalization and clock data recovery was designed in a 65 nm CMOS technology. The analog front-end adopted a low-bandwidth design to optimize the receiver's sensitivity. A decision feedback equalizer was used to recover the inter-symbol interference (ISI) introduced by the low-bandwidth front-end. In order to adapt to the inter-symbol interference introduced by different rates and process corners, the adaptive equalization of the signal was realized by combining the SS-LMS adaptive algorithm. The reference-less clock data recovery circuit used a frequency discrimination loop to widen the frequency capture range, which embedded a half-rate phase detector (PD) in the equalizer to reduce power consumption and cost. The post-simulation results show that under the parasitic capacitance of the 100 fF photodiode, the maximum gain of the receiving front end reaches 66 dBΩ, the equivalent input noise current at 25% bandwidth is 15.3 pA·Hz-1/2, and the sensitivity of the optical receiver is -14.5 dBm. When the supply voltage is 1.2 V, the overall power consumption of the optical receiver is 181.1 mW.