A parameter optimization algorithm for the incremental Σ-Δ modulator is proposed. The coefficient of the integrator in the incremental Σ-Δ modulator was optimized. The two-step search algorithm was proposed to solve and compare the possible optimal coefficient combination for many times. Based on this algorithm, the effective precision and the input sampling rate of the Σ-Δ ADC could be effectively adjusted and optimized. An 16 bit 40 kS/s incremental Σ-Δ ADC was designed. The simulation results show that the proposed optimization design algorithm can increase the ADC input sampling speed from 40 kS/s to 51 kS/s, or increase the ADC ENOB from 13.76 bit to 14.72 bit without adding additional power consumption.