Aiming at the problems of high power consumption and week shaping ability of traditional second-order noise-shaping (NS) successive approximation register analog-to-digital converters (SAR ADC), a third-order NS-SAR ADC with a hybrid error control topology of cascaded integrator feedforward (CIFF) and error feedback (EF) is proposed. A feedback capacitor was added to the system in series with the capacitor digital to analog converter (CDAC). Thus, the filter capacitor was not directly connected to the CDAC. Therefore, the feedback capacitance can be used to adjust the size of the attenuation factor to ensure that the input signal is not attenuated and the feedback signal is attenuated slightly. This EF-CIFF structure provided stronger NS capability and robustness of higher-order NTF. Furthermore, only a small gain and low power dynamic amplifier was needed to realize the residual amplification of EF and CIFF paths. The proposed NS-SAR ADC was designed in a 180 nm CMOS process. When the circuit works at 160 kS/s sampling frequency, its power consumption is only 11.3 μW at a 1.8 V supply. When the oversampling rate is 8, the ENOB is 15.6 bit.