Aiming at the requirements of SONTE OC-192, PCIE3.0, USB3.2 and other protocols for jitter tolerance and loop stability time during serial clock data recovery, a half rate phase interpolation CDR circuit with adaptive loop bandwidth adjustment was proposed. The adaptive control circuit was designed to dynamically adjust the loop bandwidth in a timely manner to achieve fast loop stability during serial signal clock recovery and improve the jitter tolerance of the clock data recovery circuit. A compensated phase interpolation controller was added to further reduce the data reception BER. The CDR circuit was designed in a 55 nm CMOS process with a data input range of 8~11.5 Gbit/s. The random code PRBS31 was used. The simulation test results showed that the stabilization time was less than 400 ns, the input jitter tolerance was more than 0.55UI@10 MHz, and the power consumption was less than 23 mW.