Based on a 0.5 μm BCD technology, a 16-bit high-precision segmented-resistance digital-to-analog converter (DAC) was designed. According to the general resistance mismatch feature in integrated circuit process, the DAC had “4+12” architecture, and it was divided into temperature coding part and binary coding part. All the resistors in this DAC were high-impedance, which reduced the mismatch in the DAC switch architecture as well as its whole power dissipation. The DAC had a compact architecture and a small layout area of 2.397 6 mm². Combined with the results after post-simulation, the layout was modified, which made the DAC have a low differential non-linearity (DNL). Moreover, its calibration part could make it lower. The test results showed that the DAC had a spurious free dynamic range of 57.72 dB, a DNL of 0.5 LSB, a INL of 1 LSB, and a power dissipation of 1.5 mW when its input was 10 kHz sine digital wave data.