A 6-bit 3.4 GS/s flash ADC was designed in a 65 nm CMOS process based on the 4 fold time-domain interpolation technique which allowed the reduction of the number of comparators from the conventional 2N-1 to 2N-2 in a N-bit flash ADC. The proposed scheme achieved effectively a 4 fold interpolation factor with simple SR-latches without extra clocking and calibration hardware overhead in the interpolated stage, where only offset between the 2N-2 comparators needed to be calibrated. The offset in SR-latches was within ±0.5 LSB in the reported ADC under a wide range of process, voltage supply, and temperature (PVT). The prototype achieved 3.4 GS/s sampling frequency with 5.4 bit ENOB at Nyquist and consumed 12.6 mW power at 1 V supply, yielding a Walden FoM of 89 fJ/(conv·step).