A continuous-rate clock and data recovery circuit was designed in 0.18 μm CMOS process. The CDR circuit included mainly a full-rate bang-bang phase frequency detector, multi-band ring voltage-controlled oscillator (VCO), charge pump and other modules. The full-rate phase detector PFD not only had good functions, but also had simple structure, low power consumption and area. Multi-band ring voltage-controlled oscillator not only had a wide tuning range, but also had a low tuning loop gain, which had settled the conflict between high oscillating frequency and low tuning gain. By using the charge pump through bootstrap reference and op amp, various non-ideal factors were reduced. Simulation results showed that the circuit was working properly, the CDR circuit could recover the NRZ data from 622 to 3 125 Mb/s. The core size was 265 μm × 786 μm. At 1.8 V supply voltage and 3 125 Mb/s input pseudo-random rate, the power consumption was 100.8 mW, the recovered data and clock jitter peak was 5.38 ps and 4.81 ps respectively.