With the development of the CMOS process, more and more attention is paid to the design of all-digital TDC, and it is used in different fields widely. In consideration of the situation, an area saving, low power consumption, low cost and transplantable TDC is presented which can be achieved with the design flow of digital ASIC. In addition, it doesn’t only perform self-calibration, but also features as simple architecture and stable measure precision. The RTL description is done by Verilog HDL firstly. Then, the gate-level netlist is synthesized by the DC followed with the VCS and Hspice simulation. Compared with the TDC available now, besides the INL is improved markedly, the TDC designed achieves wide dynamic range and stable measure precision after applied with the self-calibration method.