A correctable 12-bit C2C capacitor array hybrid structure successive approximation analog-to-digital converter (SAR ADC) is proposed, whose digital-to-analog converter (DAC) consists of a low 6-bit split C2C DAC array and a high 6-bit binary DAC array. The problem that the total capacitance is too large in the medium and high-precision binary SAR ADC and the problem that the fractional bridge capacitance of the segmented binary DAC cannot be matched with the unit capacitance can be solved by the proposed hybrid structure DAC. This structure can significantly reduce the dynamic power consumption of the entire ADC. In addition, the high terminal capacitance and the low 2-6 bit quantization capacitance are split into two equal capacitances to introduce redundancy, so that the capacitance weight of the ADC can be calibrated, which reduces the influence of capacitance mismatch and parasitic capacitance. Finally, to avoid the problem of the reset delay of the upper-level board, the method of high 6-bit DAC sampling is adopted, and a terminal capacitor of unit capacitance is introduced into the high-6-bit DAC to make up for the incompleteness of reference voltage range. The simulation results show that at 1.5 V supply voltage, the ADC's overall power consumption is only 111.84 μW, the ENOB is 12.49 bit, the SFDR is 91.46 dB, and the SNDR is 76.97 dB.