A high speed and high precision comparator for the successive approximation analog to digital converters was presented. The comparator consisted of two pre-amplifiers, a latch comparator and a buffer circuit. In order to improve the precision and speed of the comparator and reduce the power consumption, the structure of cascade and the techniques of reset and clamping had been used in the pre-amplifiers. By adding an extra positive feedback into the latch comparator, the dynamic comparator had achieved high speed and low power. Isolating the pairs of input transistors and the latch structure of latch comparator had reduced the effect of kickback noise and improved the precision. The comparator was designed and simulated in SMIC 0.18-μm CMOS process. The simulated results demonstrated that the comparator’s precision was 50 μV, the delay time was 458 ps, the power consumption was 432 μW at a clock of 800 MHz and a supply voltage of 1.8 V. The chip area was only 0.009 mm².