A 12-bit 4 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) using an energy-and area-efficient switching procedure was presented. The proposed ADC could save 95% switching energy and achieve a 4× reduction in total capacitance's area in comparison with the conventional SAR ADC. The ADC used an asynchronous control logic to avoid the use of high frequency clock, and a dynamic latch comparator was used to minimize the quiescent power dissipation. Gate voltage bootstrapped switch was used to improve the ADC's linearity. An integrated voltage reference and a buffer were employed. The proposed ADC had been simulated in the SMIC 0.18 μm CMOS technology. The post simulation results showed that, the ADC achieved a SNDR of 70.2 dB while dissipating 0.9 mW and resulting in a figure-of-merit(FOM) of 109 fJ/conversion-step at a 1.8-V supply and 4 MS/s.