Based on 65 nm CMOS process, a differential clock driver circuit that could convert a full voltage swing clock signal to a low voltage swing clock signal was proposed, which could drive the differential clock signal over an interconnection line. The problems that the traditional driver circuit had a complex structure and could not compensate the high frequency attenuation of the interconnection line were alleviated. The Spectre simulation tool was used to verify the theoretical analysis. The simulation results showed that this circuit could convert the clock signal at 1 GHz to a low voltage swing clock signal with 50% duty cycle which could be reverted to the desired rail-to-rail differential signal at the receiving terminal when the temperature range was -40℃~125℃ and the voltage range was 1.08 V~1.32 V under any process corners. The proposed circuit had a good transmission performance at high frequency.