Compared with the conventional CMOS process with P+ substrate, the performance of anti-latchup of 0.35 μm BiCMOS with P- substrate was much more worse. To improve the performance of anti-latchup of CMOS transistors, the influence of deep trench in 0.35 μm BiCMOS was studied by device simulation tools Medici and light trigger method. It’s indicated that BJT isolation deep trench in 0.35 μm BiCMOS process could improve the performance of anti-latchup of CMOS transistor. In P-substrate 0.35 μm BiCMOS process, when the light impulse width was 50 ns and the trench depths were 3,5, 7 μm respectively, the trigger currents of latchup were 3.13,6.88,1.12 times than those of 0.35 μm CMOS transistors without trench.