A DSP hard IP of ten-million-gate FPGA was designed in SMIC 65 nm CMOS process. A high performance DSP hard IP was implemented by using a full custom design. DSP hard IP mainly includes input/output logic circuits, multipliers, XYZ multiplexers and mode control units, adders, etc. Some techniques were used in the DSP hard IP to improve the speed and to reduce the chip area and circuit’s consumption. For example, half number of the partial products was reduced by 2nd order Booth encoder. The sign extend bit of partial products was decreased greatly by sign extend bit generation algorithm with logic resources and consumption curtailed accordingly. The delay of adding path of partial products was shortened by multi-types of compressors with the speed of multiplication accelerated. The operating speed of adder was expedited by the carry look-ahead adder. The DSP hard IP was simulated and verified. The chip of ten-million-gate FPGA was tested. The results showed that the function and performance of DSP hard IP met the design requirements.