Based on the analysis of LDPC decoding algorithms, a reconfigurable structure supporting 12 modes of LDPC decoding was proposed. The decoder structure could be recombined by invoking different configuration parameters, and the data cyclic shift network for different bit width could be reconfigured by shifting configuration information. With the TDMP algorithm optimized by NMS, the decoder could reduce the system hardware overhead, save the chip area, and lower the complexity of the system-level application. The decoder was designed in TSMC 0.13 μm CMOS process. Simulation results showed that the maximum clock frequency of the proposed decoder was up to 240 MHz and the maximum throughput was up to 1.568 Gbit/s. Compared with other reconfigurable structure, the presented decoder had a smaller area and could support more modes.