A 10 bit 160 kS/s cyclic ADC for image sensors was proposed. The ADC employed a 1.5 bit pipelined ADC structure, which cycled 10 times and obtained 10 bit digital code output. A two-stage operational amplifier with self-cascode structure at its input was designed to improve the amplifier gain. And the operational amplifier sharing technology was used in the ADC, so the single-ended to fully-differential circuit and the ADC could share the operational amplifier, which had reduced the area and power consumption, and had achieved the function of level shifter. Based on the 0.13 μm CMOS process, the proposed ADC had been simulated on the condition of a 3.3 V supply and 160 kHz sampling rate. The post simulation results showed that the ADC achieved an ENOB of 9.45 bit, an SNR of 59.1 dB and an SFDR of 61.26 dB. The static parameters DNL and INL was ±0.625 LSB and ±1.5 LSB respectively.